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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16682
1/65 DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The PD16682 is a LCD controller/driver that includes enough RAM capacity to drive full-dot LCD. Each chip can drive a full-dot LCD consisting of up to 132 x 65 dots. This chip is suitable for cellular phones, Japanese or Chinese-language pagers, and other devices that display Japanese or Chinese characters using either 16 x 16 or 12 x 12 dots per character.
FEATURES
* LCD controller/driver with on-chip display RAM * Able to operate using +3-V single power supply * On-chip booster circuit: switchable between 3x and 4x modes * RAM for dot displays: 132 x 65 bits * Outputs : 132 segments, 65 commons * Serial or 8-bit parallel data inputs (switchable between 80 series and 68 series MPUs) * On-chip divider resistor * Selectable bias settings (can be set as 1/9 bias or 1/7 bias) * On-chip oscillation circuit
ORDERING INFORMATION
Part number Package
Note
PD16682W-xxx PD16682P-xxx PD16682N-xxx
Wafer Chip Standard TCP (output OLB: 0.15-mm pitch), for evaluation
Note
Note
-051
Note The following four temperature gradients can be selected. -001: -0.05 % / C -002: -0.1 % / C -003: -0.15 % / C -004: 0 % / C
*
Remark
Purchasing the above chip/wafer entails exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13368EJ3V0DS00(3rd edition) Date Published March 2000 NS CP(K) Printed in Japan
The mark * shows major revised points.
(c)
1998
*
2
Data Sheet S13368EJ3V0DS00
Remark /xxx indicates active low signals.
+
1. BLOCK DIAGRAM
COM0 VDD VDD' VSS VSS' CLS TEST1 to TEST3 TEST4 to TEST5
COM63
COMS
SEG0
SEG131
Common Driver
Segment Driver 132
65 bits Register P,/S /CS1 CS2 /RD(E) /WR(R,/W) D7 (SI) D6(SCL) D5 to D0 A0 C86 /RES TESTOUT Timing Generator FRS FR CL /DOF M,/S VRS C1 , C1
+ C2 , + -
132 bits latch 132
Data Register I/O Buffer Address Decoder
Display Data RAM 132 x 65 bits
Command Decoder
D/A Converter
C3 , C3
C2- -
DC/DC Converter
OP Amp
LCD Voltage Generator
PD16682
VDD2 IRS VLCD VR HPM VLC1 VLC2 VLC3 VLC4 VLC5
PD16682
2. PIN CONFIGURATION (Pad Layout)
Chip Size: 2.66 mm x 9.84 mm
254 255 Y X 121 120
289 1 85
86
Data Sheet S13368EJ3V0DS00
3
PD16682
Table 2-1. Pad Layout (1/3) -
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pad Name DUMMY1 FRS FR CL /DOF TESTOUT VSS' /CS1 CS2 VDD' /RES A0 VSS' /WR(R,/W) /RD(E) VDD' D0 D1 D2 D3 D4 D5 D6(SCL) D7(SI) VDD VDD VDD VDD2 VDD2 VDD2 VDD2 VLCD VLCD VLCD VSS VSS VSS + C1 + C1 - C1 - C1 + C2 + C2 - C2 - C2 + C3 + C3 - C3 - C3 VSS' VDD' VDD' VRS VRS VR VR VLC1 VLC1 X [ m] -3804 -3682 -3592 -3502 -3412 -3322 -3232 -3142 -3052 -2962 -2872 -2782 -2692 -2602 -2512 -2422 -2332 -2242 -2152 -2062 -1972 -1882 -1792 -1702 -1612 -1522 -1432 -1342 -1252 -1162 -1072 -982 -892 -802 -712 -622 -532 -442 -352 -262 -172 -82 8 98 188 278 368 458 548 638 728 818 908 998 1088 1178 1268 1358 Y [ m] -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 Pad Type C B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B Pad No. 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Pad Name VLC2 VLC2 VLC3 VLC3 VLC4 VLC4 VLC5 VLC5 VSS' VSS' TEST1 TEST2 TEST3 TEST4 TEST5 VDD' M,/S CLS VSS' C86 P,/S VDD' HPM VSS' IRS VDD' DUMMY2 DUMMY3 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 X [ m] 1448 1538 1628 1718 1808 1898 1988 2078 2168 2258 2348 2438 2528 2618 2708 2798 2888 2978 3068 3158 3248 3338 3428 3518 3608 3698 3820 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 4788 Y [ m] -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1198 -1032 -940 -880 -820 -760 -700 -640 -580 -520 -460 -400 -340 -280 -220 -160 -100 -40 20 80 140 200 260 320 380 440 500 560 620 680 740 800 Pad Type B B B B B B B B B B B B B B B B B B B B B B B B B B C C A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
4
Data Sheet S13368EJ3V0DS00
PD16682
Table 2-1. Pad Layout (2/3) -
Pad No. 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 Pad Name COM1 COM0 COMS DUMMY4 DUMMY5 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 X [ m] 4788 4788 4788 4788 4023 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 Y [ m] 860 920 980 1073 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 Pad Type A A A C C A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Pad No. 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 Pad Name SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 X [ m] 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 Y [ m] 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 Pad Type A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A
Data Sheet S13368EJ3V0DS00
5
PD16682
Table 2-1. Pad Layout (3/3) -
Pad No. 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 Pad Name SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 DUMMY6 DUMMY7 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS DUMMY8 X [ m] -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -4022 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 -4788 Y [ m] 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1198 1032 940 880 820 760 700 640 580 520 460 400 340 280 220 160 100 40 -20 -80 -140 -200 -260 -320 -380 -440 -500 -560 -620 -680 -740 -800 -860 -920 -980 -1073 Pad Type A A A A A A A A A A A A A A A A A A A A A C C A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A C
Remark
Pad Type A: Pad size(Al): 47 x 105 m (TYP.)
2
Pad size (Through hole): 20 x 72 m (TYP.)
2
Bump size: 35 x 92.5 m (TYP.)
2
Bump height: 17 m(TYP.) Pad Type B: Pad size(Al): 75 x 105 m (TYP.)
2
Pad size (Through hole): 42 x 72 m (TYP.)
2
Bump size: 67 x 92.5 m (TYP.)
2
Bump height: 17 m(TYP.) Pad Type C: Pad size(Al): 118 x 105 m (TYP.)
2
Pad size (Through hole): 85 x 72 m (TYP.)
2
Bump size: 110 x 92.5 m (TYP.)
2
Bump height: 17 m(TYP.)
6
Data Sheet S13368EJ3V0DS00
PD16682
3. PIN DESCRIPTIONS
3.1 Power Supply System Pins
Pin Symbol VDD VDD2 VSS VLCD Pin Name Logic power supply pins Booster circuit power supply pins Logic/driver ground pins Driver power supply pins Pad No. 25 to 27 28 to 31 35 to 37 32 to 34 I/O -- -- -- -- Function Description Power supply pins for logic. Apply the logic power supply voltage from an external source. Power supply pins for booster circuit. Apply the booster circuit power supply voltage from an external source. Ground pins for logic and driver circuit. Connect these pins to an external ground. Power supply pins for driver. Output pins for internal booster circuit. Connect a 1- F capacitor for boosting between these pins and the GND pins. If not using the internal booster circuit, a direct driver power supply can be input. VDD' Power supply pins for fixed 10,16,51, mode pins 52,74,80, 84 VSS' Ground pins for fixed mode pins 7,13,50, 67,68,77, 82 VLC1 to VLC5 Reference power supply pins for driver Capacitor connection pins 57 to 66 -- These are reference power supply pins for the LCD driver. Connect a smoothing capacitor if an internal bias has been selected. These are capacitor connection pins for the booster circuit. Connect a 1- F capacitor. -- These ground pins are used to set the mode pins as fixed. -- These power supply pins are used to set the mode pins as fixed.
C1 , C1 C2 , C2 C3 , C3
+ +
+
-
38 to 49
--
Data Sheet S13368EJ3V0DS00
7
PD16682
3.2 Logic System Pins (1/2)
Pin Symbol P,/S Pin Name Select data input Pad No. 79 I/O Input Function Description This pin is used to select between parallel data input and serial data input. P,/S = H : Parallel data input P,/S = L : Serial data input This setting cannot be switched after power-on. For details, see 5. DESCRIPTION OF FUNCTIONS. /CS1,CS2 Chip select 8,9 Input These pins are used for the chip select signal. When /CS1 = L and CS2 = H, this signal is active and can be used for I/O of data and commands. * When connected to 80 series MPU : active low This pin connects the 80 series MPU's RD signal. Data bus output status is set when this signal is low. * When connected to 68 series MPU : active high It is used as the enable clock input pin for the 68 series MPU. /WR(R,/W) Write (read/write) 14 Input * When connected to 80 series MPU: active low This pin connects the 80 series MPU's /WR signal. Signals on the data bus are latched at the rising edge of the /WR signal. * When connected to 68 series MPU This pin is an input pin for read/write control signals. R,/W = H : Read R,/W = L : Write C86 Interface select 78 Input This pin is used to select the MPU interface. C86 = H : 68 series MPU interface C86 = L : 80 series MPU interface D0 to D5 Data bus 17 to 22 When used with a parallel interface, these pins correspond to /Output data bus bits D0 to D5. When used with a serial interface, they are pulled down internally. When used with a parallel interface, this pin corresponds to data /Output bus bit D6. When used with a serial interface, it is a serial clock input pin. Input When used with a parallel interface, this pin corresponds to data /Output bus bit D7. When used with a serial interface, it is a serial data input pin. Input This pin is connected to the LSB in the ordinary MPU address bus to distinguish between data and commands. A0 = H : Indicates that display data exists in bits D0 to D7. A0 = L : Indicates that display control commands exist in bits D0 to D7. TESTOUT /RES CLK Test output Reset Clock select 6 11 76 Output This pin is used as a test output. Leave this pin open when used for this purpose. Input Input This pin is used to perform an internal reset when at low level. This pin is used to select the valid/invalid setting for the display clock's on-chip oscillation circuit. CLS = H : On-chip oscillation circuit is valid CLS = L : On-chip oscillation circuit is invalid (external input) When CLS = L, a display clock is input via the CL pin. Input Input
/RD(E)
Read (enable)
15
Input
D6 (SCL)
Data bus/serial clock
23
D7 (SI)
Data bus/serial data input
24
A0
Data command
12
8
Data Sheet S13368EJ3V0DS00
PD16682
3.2 Logic System Pins (2/2)
Pin Symbol FR Pin Name Frame signal Pad No. 3 I/O Function Description Input This pin is used as an I/O pin for the LCD's AC conversion /Output signal. This pin is used (along with the FRS pin) for the static drive. Output This pin is used as an output pin for the static drive. This pin is used (along with the FR pin) for the static drive. M,/S Master/Slave 75 Input This pin is used to select master or slave operation mode. Timing signals required for the LCD are output during master mode and are input during slave mode to ensure synchronization of the LCD block. M,/S = H: Master operation mode M,/S = L: Slave operation mode Note the settings below, based on the status of the M,/S and CLS pins. M,/S CLS
Oscillation Circuit
FRS
Static signal
2
Power supply circuit Valid Valid
CL
FR
FRS
/DOF
H
H L
Valid Invalid
Output Output Output Output Input Input Input Output Output Output Input Input Hi-Z Hi-Z Input Input
L
H L
Invalid Invalid Invalid Invalid
CL
Display clock input
4
Input This pin is used as the display clock I/O pin. Note the settings /Output below, based on the status of the M,/S and CLS pins. M,/S CLS CL H H L L H L Output Input Input Input
When using this pin in master or slave mode, connect it to the corresponding CL pin. /DOF Blink control 5 Input /Output This pin is used to control blinking in the LCD. M,/S = H : Output M,/S = L : Input When using this pin in master or slave mode, connect it to the corresponding /DOF pin. HPM Power supply circuit select pin for LCD driver 81 Input This pin is used as a power control pin of the power supply circuit for the LCD driver. HPM = H : Normal mode HPM = L : High-power mode IRS Select pin for VLC1 regulating resistor 83 Input This pin is used to select the resistor that is used to regulate the VLC1 voltage. IRS = H : Select on-chip resistor IRS = L : Do not select on-chip resistor. The VLC1 voltage is regulated via the VR pin and an external divided resistor. Use of the on-chip resistor cannot be selected or deselected via a hard reset or via a reset command. Instead, use this pin to select the setting. TEST1 to TEST3 TEST4,TEST5 Test pins Test pins 69 to 71 72,73 Input These are test pins for IC tests. Normally, these pins should be left open.
Output These are test pins for IC tests. Normally, these pins should be left open.
Data Sheet S13368EJ3V0DS00
9
PD16682
3.3 Driver System Pins
Pin Symbol Pin Name Pad No. I/O Function Description
SEG0 to SEG131 Segment COM0 to COM63 Common
122 to 253 Output Segment output pins 87 to 118, Output Common output pins 256 to 287
COMS
Indicator common
288
Output Common output pins for indicator The same signal is output from pin 2.
VRS
Op amp inputs
53,54
Input
These are input pins for the op amp that regulates the LCD driver voltage. Leave the VRS pin open when using the on-chip power supply.
VR
55,56
When not using the on-chip power supply, a reference voltage VREG must be input. When using an external power supply, connect the VR pin to a resistor used to regulate the LCD voltage.
DUMMY1 to DUMMY5
Dummy pins
1,85,86, 120,121
--
Since these pins are not connected to any internal circuits, they should be left open when they are not being used.
10
Data Sheet S13368EJ3V0DS00
PD16682
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in the following table.
Pin Name P,/S /CS1 CS2 /RD(E) Input Input Input Input
I/O
Recommended Connection of Unused Pins Mode setting pin Connect to VSS Connect to VDD Connect to VDD (80 series interface), connect to VDD or VSS (serial interface)
Notes 1
/WR (R,/W) C86 D0 to D5 D6 (SCL) D7 (SI) A0 TESTOUT /RES CLS FR FRS /DOF M,/S CL HPM IRS TEST1 TEST2 TEST3 TEST4 TEST5
Input Input Input/Output Input/Output Input/Output Input Output Input Input Input/Output Output Input/Output Input Input/Output Input Input Input Input Input Output Output
Connect to VDD or VSS (serial interface) Mode setting pin Leave open (when using serial interface) 1 4
Data/command setting pin Leave open Connect to VDD Mode setting pin Leave open (when using master mode, M,/S = H) Leave open Leave open (when using master mode, M,/S = H) Mode setting pin Display clock Mode setting pin Mode setting pin Leave open Leave open Leave open Leave open Leave open
2
1
1 3 1 1 4 4 4
Notes 1. Connect to VDD or VSS according to the selected mode. 2. Input microcontroller output from VDD or VSS according to the selected register. 3. This pin is an output when M,/S = H and CLS = H but should otherwise be used to input the display clock. 4. These pins are pulled down to VSS in the IC.
Data Sheet S13368EJ3V0DS00
11
PD16682
5. DESCRIPTION OF FUNCTIONS
5.1 MPU Interface
5.1.1 Select interface type The PD16682 transfers data either via an 8-bit bidirectional data bus (D7 to D0) or via a serial data input (SI). The P,/S pin can be set to either high or low levels to select 8-bit parallel data input or serial data input, as shown in the table below.
P,/S H: Parallel input L: Serial input
/CS1 /CS1 /CS1
CS2 CS2 CS2
A0 A0 A0
/RD /RD Note 1
/WR /WR Note 1
C86 C86 Note1
D7 D7 SI
D6 D6 SCL
D5 - D0 D5 -D0 Note2
Notes 1. Fix this pin as either H or L. 2. High impedance
5.1.2 Parallel interface If the parallel interface has been selected (P,/S = H), setting the C86 pin either high or low determines whether to connect directly to the 80 series MPU or the 68 series MPU, as shown in the table below.
P,/S H: 68 series MPU bus L: 80 series MPU bus
/CS1 /CS1 /CS1
CS2 CS2 CS2
A0 A0 A0
/RD E /RD
D7 - D0 D7 - D0 D7 - D0
The data bus signal can be identified according to the combination of A0, /RD(E), and /WR (R,/W) signals, as shown in the table below.
Common A0 H H L L
68 Series R,/W H L H L /RD L H L H
80 Series /WR H L H L
Function
Read display data Write display data Read status Write control data (command)
12
Data Sheet S13368EJ3V0DS00
PD16682
(1) 80 Series Parallel Interface When 80 series parallel data transfer has been selected, data is written to the PD16682 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-1. 80 Series Interface Data Bus Status -
/CS1 (CS2=H)
/WR
/RD
Hi-Z DBn Data write Valid data Data read
Hi-Z
(2) 68 Series Parallel Interface When 68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. During the data read operation, the data bus enters the output status when the R,/W signal is H, outputs valid data at the rising edge of the E signal, and enters the high-impedance state at the falling edge of the R,/W signal (R,/W = L) Figure 5-2. 68 Series Interface Data Bus Status -
/CS1 (CS2=H)
R,/W
E
Hi-Z
Hi-Z DBn Invalid data Valid data
Hi-Z
Data Sheet S13368EJ3V0DS00
13
PD16682
5.1.3 Serial interface If the serial interface has been selected (P,/S = L) and if the chip is in the active state (/CS1 = L and CS2 = H), both serial data input (SI) and serial clock input (SCL) can be received. The serial interface includes an 8-bit shift register and a 3-bit counter. Serial data is captured at the rising edge of the serial clock and is clocked in via the serial data input pins in sequence from D7 to D0. At the rising edge of the eighth serial clock, data is converted to 8-bit parallel data. Input via the A0 pin can be used to determine whether the input serial data is display data or a command (display data when A0 = H, command when A0 = L). The timing for reading and identifying input via A0 occurs at the rising edge of the "eighth x n" serial clock once the chip's status is active. A serial interface signal chart is shown below. Figure 5-3. Serial Interface chart -
/CS1 CS2 SI SCL A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Remarks1. When the chip's status is inactive, the shift register and counter are both reset to their initial values. 2. Data cannot be read when using the serial interface. 3. For the SCL signal, caution is advised concerning the wire's terminating reflection and noise from external sources. We recommend to check the operation on the actual equipment. 5.1.4 Chip select The PD16682 has two chip select pins (/CS1 and CS2). The MPU interface or serial interface can be used only when /CS1 = L and CS2 = H. When the chip select pin is inactive, D7 to D0 are set to high impedance (invalid) and input of A0, /RD, or /WR is invalid. If the serial interface has been selected, the shift register and counter are both reset. 5.1.5 Display data RAM and internal register access Access to the PD16682 from the MPU supports high-speed data transfers since the cycle time (tCYC) is met and there is no need for wait time. When data transfer occurs between the PD16682 and the MPU, the data is held in a bus holder belonging to the internal data bus and is written to the display data RAM before the next data write cycle. When the MPU reads the contents of the display data RAM, the data read during the first data read cycle (dummy cycle) is first held in the bus holder and is read from the bus holder to the system bus during the next data read cycle. Note with caution that, due to constraints on the read sequence for the display data RAM, when the address is set, the data is not output from the address specified by the next read command but rather is output to the address specified during the second data read operation. Consequently, one dummy read operation is strictly required after setting an address or after a write cycle. Figure 5-4 illustrates this situation.
14
Data Sheet S13368EJ3V0DS00
PD16682
Figure 5-4. Write and Read Operations -
Writing MPU
/WR
DATA
N
N+1
N+2
N+3
Internal Timing
Latch
BUS Holder Write Signal
N
N+1
N+2
N+3
Reading MPU
/WR
/RD
DATA
N
N
n
n+1
Internal Timing
Address Preset Read Signal Column Address BUS Holder Address Set #n
Preset N
increment N+1
N+2
N
n
n+1
n+2
Dummy Read
Data Read #n
Data Read #n+1
Data Sheet S13368EJ3V0DS00
15
PD16682
6. DISPLAY DATA RAM
6.1 Display Data RAM This is the RAM that is used to store the display's dot data. The RAM configuration is 65 (8 pages x 8 bits + 1) x 132 bits. Any specified bit can be accessed by selecting the corresponding page address and column address. As is shown in Figure 6-1 below, the display data (D7 to D0) from the MPU corresponds to the common direction in the LCD, so that if a multiple set of PD16682 chips is used, there are fewer constraints on transfers of display data and relatively more freedom for display configurations. The MPU accesses the display data RAM for read/write operations via the I/O buffer, and these operations are independent of the LCD driver signal read operations. Therefore, there are absolutely no adverse effects (such as flicker) in the display when display data RAM is accessed asynchronously in relation to the LCD contents. Figure 6-1. LCD Data and LCD Display - LCD data
D0 D1 D2 D3 D4 ... 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 ...
LCD display
6.2 Page Address Circuit The page address set command specifies the page address in the display data RAM, as is shown in Figure 6-2. To access a different page, simply specify a different page address using this command. Page address 8 (D3,D2,D1,D0 = 1,0,0,0) is a RAM area that is used exclusively for indicator, so only display data D0 is valid.
6.3 Column Address Circuit The column address set command specifies the column address in the display data RAM, as is shown in Figure 6-2. The specified column address is incremented each time a display data read or write command is input, so the MPU is able to successively access display data. Incrementation of the column address stops at 83H. The column address and page address are mutually independent, which means that to switch from column 83H on page 0 to column 00H on page 1, both the page address and column address must be separately specified again. Also, as is shown in Table 6-1, the ADC command (segment driver direction select command) can be used to invert the correspondence between the display data RAM's column address and segment output. This reduces the number of IC layout constraints that are imposed when setting up the LCD module. Table 6-1. Relation between Display Data RAM Column Address and Segment Output -
SEG Output ADC (D0) "0" "1" SEG0 00H 83H Column Address Column Address SEG131 83H 00H
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Data Sheet S13368EJ3V0DS00
PD16682
6.4 Line Address Circuit As is shown in Figure 6-2, the line address circuit specifies the line address that corresponds to a COM output for displaying the contents of display data RAM. The display start line address set command usually specifies the highest line in the display (corresponding to the COM0 output when in normal mode or the COM63 output when in inverted mode). Thus, there are 65 lines in the direction of incrementation of line address starting from the specified display start line address. The screen can be scrolled by dynamically changing the line address via the display start line address set command. Figure 6-2. Specification of Display Start Line Address in Display Data RAM -
Page Address D3 D2 D1 D0 Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
83 00 82 01 81 02 80 03 7F 04 7E 05 7D 06 7C 07
Line Address Common output status : Normal mode 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS Note
0
0
0
0
Page0
0
0
0
1
Page1
0
0
1
0
Page2
0
0
1
1
Page3
Start
0
1
0
0
Page4
0
1
0
1
Page5
0
1
1
0
Page6
0
1
1
1
Page7
1
0
0
0
Page8
SEG124 07 7C SEG125 06 7D SEG126 05 7E SEG127 04 7F SEG128 03 80 SEG129 02 81 SEG130 01 82 SEG131 00 83 D0 D0
Column Address
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
LCD
1
Note COMS accesses the 65th line regardless of the display start line address.
Data Sheet S13368EJ3V0DS00
Out
ADC
0
17
PD16682
6.5 Display Data Latch Circuit The display data latch circuit is used for temporary storage of display data that has been output to the LCD driver circuit from the display data RAM. The commands that are used to set normal/inverted display modes, display ON/OFF status, and display all ON/OFF status are commands that control data in this latch so that there is no modification of the data in the display data RAM.
7. OSCILLATION CIRCUIT
This is a CR-type oscillation circuit that generates the display clock. The oscillation circuit is valid only when CLS = H. When CLS = L, oscillation is stopped and the display clock is input via the CL pin.
8. DISPLAY TIMING GENERATOR
The display timing generator generates timing signals from the display clock to the line address circuit and the display data latch circuit. Display data is latched into the display data latch circuit in synch with the display clock and is output via segment driver output pins. Reading of the display data is completely independent of the MPU's accessing of the display data RAM. Consequently, there are no adverse effects (such as flicker) on the LCD panel even when the display data RAM is accessed asynchronously in relation to the LCD contents. The internal common timing and LCD's AC conversion signal (FR) are both generated from the display clock. As is shown in Figure 8-1, a drive waveform based on the two-frame AC drive method is generated for the LCD driver circuit. If a multiple set of PD16682 chips is used, the display timing signals (FR, CL, and /DOF) for the slave side must be supplied from the master side.
Operation Mode Master (M,/S = H) On-chip oscillation circuit is valid (CLS = H) On-chip oscillation circuit is invalid (CLS = L) Slave (M,/S = L) On-chip oscillation circuit is invalid (CLS = H) On-chip oscillation circuit is invalid (CLS = L)
FR Output Output Input Input
CL Output Input Input Input
/DOF Output Output Input Input
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Data Sheet S13368EJ3V0DS00
PD16682
Figure 8-1. Drive Waveform when Using Two-Frame AC Drive Method -
1Frame 1 2 3 4 5 6 7 8 63 64 65 1 2 3 4 5 6 7 8 63 64 65
CL FR RAM DATA VLC1 VLC2 VLC3 SEG1 VLC4 VLC5 VSS
VLC1 VLC2 VLC3 COM0 VLC4 VLC5 VSS VLC1 VLC2 VLC3 COM1 VLC4 VLC5 VSS
VLC1 VLC2 VLC3 COMS VLC4 VLC5 VSS
Data Sheet S13368EJ3V0DS00
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PD16682
9. COMMON OUTPUT STATUS SELECT CIRCUIT
With the PD16682, the common output status select command can be used to set the scan direction for COM outputs (see Table 9-1). As a result, there are fewer IC layout constraints when setting up the LCD module. Table 9-1. Setting of Scan Direction for COM Outputs -
Status Normal (forward) Inverted (reverse) COM Scan Direction COM0 COM63 COM63 COM0
10. POWER SUPPLY CIRCUIT
10.1 Power Supply Circuit The power supply circuit, which supplies the voltage needed to drive the LCD, includes a booster circuit, voltage regulator circuit, and voltage follower circuit. The power control set command is used to control the ON/OFF status of the power supply circuit's booster circuit, voltage regulator circuit (V regulator circuit), and voltage follower circuit (V/F circuit). This makes it possible to jointly use an external power supply along with certain functions of the on-chip power supply. Table 10-1 shows the function that controls the 3-bit data in the power control set command and Table 10-2 shows a reference chart of combinations. Table 10-1. Control Values Set to Bits in Power Control Set Command -
Item H D2 D1 D0 Booster circuit control bit Voltage regulator circuit control bit Voltage follower circuit control bit ON ON ON Status L OFF OFF OFF
Table 10-2. Reference Chart of Combinations -
Use Status D2 D1 D0 Booster Circuit <1> Use on-chip power supply <2> Use V regulator circuit and V/F circuit only <3> Use V/F circuit only <4> Use External power supply only L L L L H L x x x x
+ - +
V Regulator Circuit {
V/F Circuit
External Power Supply Input
Boosterrelated Pin Used
H
H
H
{ x
{
VDD2
L
H
H
{
{
VLCD
Open
{ x
- +
VLC1 VLC1 to VLC5
Open Open
Remarks 1. The booster-related pins are indicated as pins C1 , C1 , C2 , C2 , C3 , and C3 . 2. Although combinations other than those shown above are possible, they have no practical uses and therefore cannot be recommended.
-
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Data Sheet S13368EJ3V0DS00
PD16682
10.2 Booster circuit 3x and 4x booster circuits have been incorporated in chip to generate the current driving the LCD. When using the internal power supply, connect the booster-related capacitor between C1 and C1 , C2 and C2 , and C3 and C3 . Also, connect the level stabilization-related capacitor between VLCD and VSS and set D2 high to boost the potential between VDD2 and VSS from 3 to 4 times. Since the booster circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. The relation between the boosted voltage and the potential is described below. The C1 , C1 , C2 , C2 , C3 , C3 , and VDD2 pins all relate to the booster circuit, so the wire impedance should be minimized. Figure 10-1. 3x and 4x Booster Circuits -
VLCD = 4VDD2 = 12 V (During 4x boost mode) VLCD = 3VDD2 = 9 V (During 3x boost mode)
+ - + - + - + - + - + -
VDD2 = 3 V VSS = 0 V
Caution When set to 3x boost mode, connect booster-related capacitors between C2 and C3 and between C1 and C1 .
+ + -
-
10.3 Voltage Regulator Circuit The boost voltage that was generated at VLCD is output via the voltage regulator circuit as the LCD drive voltage VLC1. Since the PD16682 has a 64-level electronic volume function and an on-chip resistor for VLC1 voltage regulation, various components can be used to configure a highly accurate voltage regulator circuit.
10.3.1 Use of on-chip resistor for VLC1 voltage regulation The on-chip resistor for VLC1 voltage regulation and the electronic volume function can be used to regulate the darkness of the LCD contents, not only by adding an external resistor but also by controlling the LCD drive voltage VLC1 by using commands only. The VLC1 voltage can be determined using equation 10-1 as within the range of VLC1 < VLCD.
Data Sheet S13368EJ3V0DS00
21
PD16682
Equation 10-1. -
VLC1 = (1 + Rb )VEV Ra
The equation for determining VEV varies according to the product code (temperature gradient).
VEV = VEV VEV VEV 162 (1 - )VREG (-001 code, -0.05 % / C) 203 162 162 (1 - )VREG (-002 code, -0.1 % / C) = 178 162 162 (1 - )VREG (-003 code, -0.15 % / C) = 221 162 )VREG (-004 code, 0 % / C) = (1 - 162
+ VLC1 - VEV (Constant voltage source + electronic volume) Rb
Ra
VREG is the IC's internal constant voltage source, whose voltage values (at TA = 25 C) are listed in Table 10-3 below. Table 10-3. VREG -
Product Code -001 -002 -003 -004 Temperature Gradient (%/C) -0.05 -0.1 -0.15 0 VREG (V) 2.08 1.84 1.62 2.39
Given as the electronic volume command value, when data is set to the 6-bit electronic volume register, one of 64 statuses is set. Values for corresponding to various electronic volume register settings are listed in Table 10-4 below. Table 10-4. Values Determined by Electronic Volume Register Settings -
D5 0 0 0 0 : 1 1 1 D4 0 0 0 0 : 1 1 1 D3 0 0 0 0 : 1 1 1 D2 0 0 0 0 : 1 1 1 D1 0 0 1 1 : 0 1 1 D0 0 1 1 1 : 1 0 1 63 62 61 60 : 2 1 0
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Data Sheet S13368EJ3V0DS00
PD16682
Rb/Ra is an on-chip resistance factor used for the VLC1 voltage regulator. This factor can be controlled among eight levels using the VLC1 voltage regulator resistance factor set command. Table 10-5 lists reference values for (1+Rb/Ra) which are set when 3-bit data is set to the VLC1 voltage regulator resistance factor register. Table 10-5. Reference Values for (1 + Rb/Ra) -
Register D3 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Reference Value
10.3.2 When using external resistor (not using on-chip resistor for VLC1 voltage regulator) Instead of using the on-chip resistor for the VLC1 voltage regulator (IRS pin = L), resistors (Ra' and Rb') can be added between VSS and VR and between VR and VLC1 to set the LCD power supply voltage VLC1. In such cases, the electronic volume function can be used to control the LCD power supply voltage VLC1 using commands to regulate the darkness of the LCD contents. The VLC1 voltage can be determined using equation 10-2 as within the range of VLC1 < VLCD. Equation 10-2. -
VLC1 = (1 + Rb' )VEV Ra'
The equation for determining VEV varies according to the product code (temperature gradient).
VEV = VEV VEV VEV 162 (1 - )VREG (-001 code, -0.05 % / C) 203 162 162 (1 - )VREG (-002 code, -0.1 % / C) = 178 162 162 (1 - )VREG (-003 code, -0.15 % / C) = 221 162 )VREG (-004 code, 0 % / C) = (1 - 162
+ VLC1 - VEV (Constant voltage source + electronic volume) VR Rb' VLC1
Ra'
Data Sheet S13368EJ3V0DS00
23
PD16682
10.4 Op Amp Control for Level Power Supply The PD16682's on-chip power supply circuit is designed for low power consumption (HPM = H). Consequently, display quality may be diminished when a large LCD device or panel is used. In such cases, the display quality can be improved by setting HPM = L (high-power mode). We recommend that you check the actual display quality before deciding whether or not to use high-power mode. If setting high-power mode still does not sufficiently improve the display quality, the LCD driver's power supply must be provided from an external source.
10.5 Command Sequence for Stepping Down On-chip Power Supply As shown in the following command sequence, we recommend that you set low power mode and turn off the power before stepping down the on-chip power supply.
Step
Description (Command, Status) D7 1 1 D6 0 0 D5 1 1
Command Address D4 0 0 D3 1 0 D2 1 1 D1 1 0 D0 0 1 Power save command (compound)
Step1 Step2 End
Display OFF Display all ON On-chip power supply OFF
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Data Sheet S13368EJ3V0DS00
PD16682
10.6 Use Example of Power Supply Circuit
A) 4x boost (normal mode/using on-chip power supply) To logic system power supply VDD IRS HPM VLCD + C4 VDD2 VRS Open
+
B) 3x boost
To booster circuit power supply
VLCD C4
VR
Open
C1+ + C1 C1 + C2 + C2
-
VLC1
+
C1 + C1
+
VLC2 +
C1 Open
-
VLC3 +
C2 + C2-
VLC4 C2 C3 + + C3 + C3
- -
+ VLC5 + C2 C3+
Open
C3
-
VSS VSS
Note Leave the C2 and C3 pins open. Remark C1 = C2 = C3 = C4 = 1.0 F
+
-
Data Sheet S13368EJ3V0DS00
25
PD16682
11. RESET CIRCUIT
In the PD16682, when the /RES input is at low level, a reset is executed. The reset (default) settings are described below. 1. Display OFF 2. Normal display direction 3. ADC select: normal direction (ADC command D0 =L) 4. Power control register: (D2,D1,D0) = (0,0,0) 5. Data cleared from register in serial interface 6. LCD power supply bias: 1/9 bias 7. Read modify write OFF 8. Power save canceled 9. SEG/COM output: VSS 10. Static indicator OFF Static indicator register: (D2,D1) = (0,0) 11. Display start line: set to line 1 12. Column address: set to address 0 13. Page address: set to page 0 14. Common output status: Normal 15. Canceled mode set for on-chip resistance factor for VLC1 voltage regulator VLC1 voltage regulator resistance factor register (D2,D1,D0) = (0,0,0) 16. Canceled mode set for electronic volume register Electronic volume register: (D5,D4,D3,D2,D1,D0) = (1,0,0,0,0,0) 17. Test mode canceled 18. Display all OFF (display all ON/OFF command, D0 = L) Only items 1, 7, and 9 to 18 above are executed when a reset command is used.
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Data Sheet S13368EJ3V0DS00
PD16682
12. COMMANDS
The PD16682 uses a combination of A0, /RD(E), and /WR(R,/W) to identify data bus signals. Command interpretation and execution is performed using internal timing that does not depend on any external clock. The 80 series MPU interface activates commands using low pulse input to the /RD pin during read and activates commands using low pulse input to the /WR pin during write. The 68 series MPU interface sets read mode using high-level input to the R,/W pin and sets write mode using low-level input to the R,/W pin. The command is activated using high pulse input to the E pin. Thus, the 68 series MPU interface differs from the 80 series MPU interface in that /RD(E) is at high level during status read and display data read operations, as is shown in the command descriptions and command table. Command descriptions using an 80 series MPU interface are shown below. If the serial interface has been selected, data is input sequentially starting from D7.
12.1 Display ON/OFF This command specifies the display's ON/OFF status.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 1
D0 1 0
Setting Display ON Display OFF
Executing the display all ON command while the display is OFF sets power save (low power) mode. For details, see 12.20 Power Save (Compound Command). When the display is OFF, output via all driver outputs (segment and common) is at VSS level.
12.2 Display Start Line Set This command specifies the address of the display start line in the display data RAM, as was shown in Figure 6-2. The display area extends from the specified line address in the direction of higher line addresses, and includes the number of lines that corresponds to the display duty setting. The display can be smoothly scrolled vertically by using this command to dynamically modify the specified line addresses. For details, see 6.4 Line Address Circuit.
A0 0
E, /RD 1
R,/W, /WR 0
D7 0
D6 1
D5 0 0 0
D4 0 0 0
D3 0 0 0
D2 0 0 0
D1 0 0 1
D0 0 1 0
Line Address 0 1 2
1 1
1 1
1 1
1 1
1 1
0 1
62 63
Data Sheet S13368EJ3V0DS00
27
PD16682
12.3 Page Address Set This command specifies the page address corresponding to the row address when accessing the display data RAM from the MPU side, as was shown in Figure 6-2. The specified bit in display data RAM can be accessed by selecting the corresponding page address and column address. If the page address is changed, the display mode does not change. For details, see 6.2 Page Address Circuit.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 1
D3 0 0 0
D2 0 0 0
D1 0 0 1
D0 0 1 0
Page Address 0 1 2
0 1
1 0
1 0
1 0
7 8
12.4 Column Address Set This command specifies the column address in display data RAM, as was shown in Figure 6-2. The column address is set in a (basically continuous) series of two specifications, one for the high-order four bits and another for the low-order four bits. The column address is automatically incremented (+1) each time the display data RAM is accessed, so the MPU is able to continuously read or write display data. Incrementation of the column address stops at 83H. At that point the page address can no longer be continuously modified. For details, see 6.3 Column Address Circuit.
A0 0
E, /RD 1
R,/W, /WR 0
D7 0
D6 0
D5 0
D4 1 0
D3 A7 A3
D2 A6 A2
D1 A5 A1
D0 A4 A0
A7 0 0 0
A6 0 0 0
A5 0 0 0
A4 0 0 0
A3 0 0 0
A2 0 0 0
A1 0 0 1
A0 0 1 0
Column Address 0 1 2
1 1
0 0
0 0
0 0
0 0
0 0
1 1
0 1
130 131
28
Data Sheet S13368EJ3V0DS00
PD16682
12.5 Status Read
A0 0
E, /RD 0
R,/W, /WR 1
D7 0
D6 ADC
D5 ON/OFF
D4 RESET
D3 0
D2 0
D1 0
D0 0
ADC
This indicates the relation between the column address and the segment driver. 0: Inverted (column address 131-n SEGn) 1: Normal (column address n SEGn)
ON/OFF
ON/OFF: Indicates the display's ON/OFF status. 0: Display ON 1: Display OFF (This is the opposite of the display ON/OFF command's polarity.)
RESET
This indicates whether or not the system is undergoing a reset via the /RES signal or the reset command. 0: Operating mode 1: Reset in progress
12.6 Display Data Write This command writes 8 bits of data to the specified address in display data RAM. After this data has been written, the column address is automatically incremented (+1), which enables the MPU to continuously write display data.
A0 1
E, /RD 1
R,/W, /WR 0
D7
D6
D5
D4
D3
D2
D1
D0
Write Data
12.7 Display Data Read This command reads 8 bits of data from the specified address in display data RAM. After this data has been read, the column address is automatically incremented (+1), which enables the MPU to continuously read several words of data. A single dummy read operation is required immediately after the column address has been set. For details, see 5.1.5 Display data RAM and internal register access. Note that the display data cannot be read when using a serial interface.
A0 1
E, /RD 0
R,/W, /WR 1
D7
D6
D5
D4
D3
D2
D1
D0
Read Data
Data Sheet S13368EJ3V0DS00
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PD16682
12.8 ADC Select (Segment Driver Direction Select) This command inverts the relation between the display data RAM's column address and segment driver output, as was shown in Figure 6-2. Consequently, the segment driver output pin number can be inverted by this command. For details, see 6.3 Column Address Circuit. Incrementation (+1) of the column address when display data is either written or read is performed according to the column address shown in Figure 6-2. This command should be input during initialization.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 1
D3 0
D2 0
D1 0
D0 0 1
Setting Normal (forward direction) Inverted (reverse direction)
12.9 Display Normal/Inverted This command can be used to invert the display ON/OFF control without replacing any of the display data RAM contents. The display data RAM contents are retained when this command is executed.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 1
D0 0
Setting RAM data: H LCD ON potential (normal)
1
RAM data: L LCD ON potential (inverted)
12.10 Display All ON/OFF This command can be used to set the display all ON status forcibly regardless of the display data RAM contents. The display data RAM contents are retained when this command is executed. This command takes priority over the display normal/inverted command.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 1
D1 0
D0 0 1
Setting Normal display mode Display all ON
12.11 LCD Bias Set This command selects the bias setting of the voltage required to drive the LCD. This command is valid when the power supply circuit's V/F circuit is operating.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 0
D3 0
D2 0
D1 1
D0 0 1 1/9 bias 1/7 bias
Setting
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Data Sheet S13368EJ3V0DS00
PD16682
12.12 Read Modify Write This command is used in a pair with the end command. When this command has been input, the column address is not changed by the display data read command and can be incremented (+1) only by the display data write command. This status is retained until an end command is input. Once an end command has been input, the column address returns to the address that was used when the read modify write command was input. This function can be used to lighten the burden on the MPU when repeatedly modifying data in special display areas such as the blinking cursor.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 0
Caution The commands other than the display data read/write commands can be used even during read modify write mode. However, the column address set command cannot be used. Figure 12-1. Sequence for Cursor Display -
Page address set
Column address set
Read modify write
Dummy read
Data read
Data processing
Data write
No
Changes completed?
Yes
End
Data Sheet S13368EJ3V0DS00
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PD16682
12.13 End This command is used to cancel read modify write mode and return to the address that was used during column address mode reset.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 1
D4 0
D3 1
D2 1
D1 1
D0 0
Figure 12-2. End -
Return
Column Address
N
N+1
N+2
N+3
N+m
N
Read Modify Write Mode Set
End
12.14 Reset This command initializes the contents of the various command registers. The display data RAM is not affected. For details, see 11. RESET CIRCUIT. The reset operation is performed after the reset command has been input.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 0
The reset that occurs when the power supply is applied is performed by issuing a reset signal to the /RES pin. It cannot be used as a substitute for the reset command.
12.15 Common Output Status Select This command can be used to select the scan direction for the COM output pins. For details, see 9. COMMON OUTPUT STATUS SELECT CIRCUIT.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 0
D4 0
D3 0 1
D2 X
D1 X
D0 X
Setting Normal (forward) Inverted (reverse)
Remark
X: Don't care
Status Normal (forward) Inverted (reverse) COM0 COM63
Selected status COM63 COM0
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Data Sheet S13368EJ3V0DS00
PD16682
12.16 Power Control Set This command is used to set the function of the power supply circuit. For further description, see 10. POWER SUPPLY CIRCUIT.
A0 0 E, /RD 1 R,/W, /WR 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 1 X X X X D1 X X 0 1 X X D0 X X X X 0 1 Selected Status Booster circuit: OFF Booster circuit: ON V regurator circuit:OFF V regurator circuit: ON V/F circuit: OFF V/F circuit: ON
Remark X: Don't care 12.17 Set On-chip Resistance Factor for VLC1 Voltage Regulator This command is used to set the on-chip resistance factor for the VLC1 voltage regulator. For details, see 10.3 Voltage Regulator Circuit.
A0 0 E, /RD 1 R,/W, /WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 (1+Rb/Ra) 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
12.18 Electronic Volume (Two-Byte Command) This command can be used to control the LCD drive voltage VLC1 (which is output from the on-chip LCD power supply's voltage regulator circuit) to regulate the darkness of the LCD contents. This command is a two-byte command that is used in a pair with the electronic volume mode set command and the electronic volume register set command, so be sure to use both commands consecutively. 12.18.1 Electronic volume mode set command (first byte) Once this command is input, the electronic volume register set command becomes valid. And once the electronic volume mode has been set, any command other than the electronic volume register set command cannot be used. This restriction is cleared once data has been set to the register by the electronic volume register set command.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 0
D4 0
D3 0
D2 0
D1 0
D0 1
Data Sheet S13368EJ3V0DS00
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PD16682
12.18.2 Electronic volume register set command (second byte) When six bits of data are set to the electronic volume register by this command, the LCD drive voltage VLC1 is set to one of 64 possible voltage values. Once this command has been input and the electronic volume register has been set, electronic volume mode is canceled.
A0 0
E, /RD 1
R,/W, /WR 0
D7 X X X
D6 X X X
D5 0 0 0
D4 0 0 0
D3 0 0 0
D2 0 0 0
D1 0 0 1
D0 0 1 0
VLC1 Smaller value
X X X X 1 1 1 1 1 1 1 1 1 1 0 1 Larger value
Remark X: Don't Care Figure 12-3. Sequence of Electronic Volume Register Set Operations -
Electronic volume mode set
Electronic volume register set Cancel electronic volume mode
No
Changes completed?
Yes
12.19 Static Indicator (Two-Byte Command) This command is used to control the indicator display for the static drive system. Only this command can control the static indicator display, and it operates independently of other display control commands. One of the electrodes for the static indicator's LCD driver is connected to the FR pin and the other is connected to the FRS pin. We recommend that these status indicator electrodes be implemented in a pattern that is separate from the electrodes used for the dynamic drive. The LCD and the electrodes themselves may deteriorate if the patterns are laid out too close to each other. The static indicator ON command is a two-byte command that is used in a pair with the static indicator register set command, so be sure to use both commands consecutively. (The static indicator OFF command is a one-byte command.)
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Data Sheet S13368EJ3V0DS00
PD16682
12.19.1 Static indicator ON/OFF When the static indicator ON command is input, the static indicator register set command becomes valid. Once the static indicator ON command has been input, any command other than the static indicator register set command cannot be used. This restriction is cleared once data has been set to the register by the static indicator register set command.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 0
D5 1
D4 0
D3 1
D2 1
D1 0
D0 0 1
Static Indicator OFF ON
12.19.2 Static indicator register set This command sets data to the two-bit static indicator register and then sets the static indicator to blink mode.
A0 0
E, /RD 1
R,/W, /WR 0
D7 X
D6 X
D5 X
D4 X
D3 X
D2 X
D1 0 0
D0 0 1
Static Indicator OFF ON (blinks at onesecond interval)
1
0
ON (blinks at halfsecond interval)
1
1
ON (always ON)
Figure 12-4. Sequence of Static Indicator Register Set Operations -
Static indicator ON Static indicator register set Cancel static indicator mode
No
Changes completed?
Yes
12.20 Power Save (Compound Command) The current consumption can be greatly reduced by entering the power save status by inputting the display all ON command while the display is in OFF mode. The power save (low power) mode includes two modes; sleep mode and standby mode. Turning the static indicator OFF sets sleep mode and turning it ON sets standby mode. During either sleep mode or standby mode, the display data is retained as it was before the power save function was activated. Also, access to the display data RAM from the MPU is possible during either mode. Use the display all OFF command to cancel power save mode.
Data Sheet S13368EJ3V0DS00
35
PD16682
Figure 12-5. Power Save -
Static indicator OFF Static indicator ON
Power save (compound command)
Static indicator ON Sleep mode Reset command Standby mode
Power save OFF (Display all OFF command)
Power save OFF (Display all OFF command)
Cancel sleep mode
Cancel standby mode
12.20.1 Sleep mode During this mode, all LCD operations are stopped and there is no access from the MPU, so current consumption can be reduced almost as low as the static current level. The internal status during sleep mode is as follows. (1) The oscillation circuit and LCD power supply circuit are stopped. (2) All LCD drive circuits are stopped and both segment and common driver outputs output at the VSS level. 12.20.2 Standby mode During this mode, all duty LCD display system operations are stopped and only the static drive system for the indicators operate, which reduces the current consumption to the minimum amount needed for static drive. The internal status during standby mode is as follows. (1) The LCD's power supply circuit is stopped. The oscillation circuit operates. (2) The duty drive system's LCD drive circuit is stopped and both segment and common driver outputs output at the VSS level. The static drive system operates. When a reset command is executed while in standby mode, it sets sleep mode. Remarks 1. If you are using an external power supply, we recommend that you stop the external power supply circuit's functions when activating the power save function. For example, if you are using an external divided resistor circuit to provide LCD drive voltage at different levels, we recommend that you add a circuit to cut the current flowing on the divided resistor circuit while the power save function is being activated. 2. The PD16682 includes the /DOF pin which is used to control blinking LCD displays is set to low level when activating the power save function. The output from /DOF can be used to stop the external power supply circuit's function. 3. When the display has been set to OFF mode, executing the display all ON command sets power save mode no matter which command is entered afterward. 36
Data Sheet S13368EJ3V0DS00
PD16682
12.21 NOP This command is used to set NOP (Non-Operation) mode.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 1
D0 1
12.22 Test This command is used for IC testing. Do not use this command. If you use it by mistake, either set the /RES input low or use the reset command or NOP command to cancel the test command setting.
A0 0
E, /RD 1
R,/W, /WR 0
D7 1
D6 1
D5 1
D4 1
D3 X
D2 X
D1 X
D0 X
Remark X: Don't care
Data Sheet S13368EJ3V0DS00
37
PD16682
Table 12-1. List of PD16682 Commands (1/2) -
Command A0 Display ON/OFF 0 /RD 1 /WR 0 D7 1 Command code D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0 1 Display start line set 0 1 0 0 1 Display start address Sets LCD's ON/OFF status 0: OFF, 1: ON Sets display RAM's display start line address Page address set 0 1 0 1 0 1 1 Page address Sets display RAM's page address Column address set (high-order bits) 0 1 0 0 0 0 1 High-order column address Sets high-order four bits of display RAM's column address Column address set (low-order bits) 0 1 0 0 0 0 0 Low-order column address Sets low-order four bits display RAM's column address Status read Display data write Display data read ADC select 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 Status 0 Write data Read data 0 0 0 0 0 1 0 0 0 Read status information Writes to display RAM Reads from display RAM Sets correspondence of SEG output to display RAM address 0: Normal, 1: Inverted Display normal/inverted Display all ON/OFF 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 Sets normal/inverted direction of display Sets display all ON 0: Normal display, 1: All ON LCD bias set 0 1 0 1 0 1 0 0 0 1 0 1 Sets the bias setting of the LCD drive voltage 0: 1/9 bias, 1: 1/7 bias Read modify write 0 1 0 1 1 1 0 0 0 0 0 Specifies incrementation of the column address During write: +1, During read: 0 End 0 1 0 1 1 1 0 1 1 1 0 Cancels read modify write Reset Selects scan direction for COM outputs 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 0 X X 1 X X 0 X X Sets an internal reset Selects scan direction for COM outputs 0: Normal (forward), 1: Inverted (reverse) Function
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Data Sheet S13368EJ3V0DS00
PD16682
Table 12-1. List of PD16682 Commands (2/2) -
Command A0 Power control set 0 /RD 1 /WR 0 D7 0 Command code D6 0 D5 1 D4 0 D3 1 D2 D1 D0 Selects operation mode of internal power supply Sets VLC1 output voltage to electronic volume register Electronic volume mode set Electronic volume register set Static indicator ON/OFF Static indicator register set Power save Compound command for setting display OFF and all display ON NOP 0 1 0 1 1 1 0 0 0 1 1 Command for NonOperation mode Test 0 1 0 1 1 1 1 X X X X Command used for IC testing Caution Do not use this command. 0 1 0 X X X X X X Mode 0 1 0 1 0 1 0 1 1 0 0 1 Sets ON mode 0: OFF, 1: ON 0 1 0 X X Electronic volume value 0 1 0 1 0 0 0 0 0 0 1 Sets VLC1 output voltage to electronic volume register 0 1 0 0 0 1 0 0 Resistance factor setting Selects on-chip resistance factor for (Ra/Rb) Function
Operation mode
Remark
X: Don't care
Data Sheet S13368EJ3V0DS00
39
PD16682
13. ACCESS PROCEDURE
13.1 Initialization setting example (from power application to display ON) Although a VSS level is output from the SEG and COM LCD drive output pins when power is applied to the IC, if there is electric charge remaining in the smoothing capacitor connected between the driver reference power supply pins (VLC1 to VLC5) and VSS, or if the DC/DC converter's booster voltage does not reach the prescribed booster potential or the levels of the reference power supplies (VLCn) do not reach the prescribed voltages when power is applied, abnormalities such as a temporary screen blackout may occur when the display turns on. The following power application flow is recommend to avoid the occurrence of abnormal operation when the power is turned on.
Power supply between VDD/VDD2 and VSS ON when /RES pin in L state
Power supply stabilization
Reset state release (/RES pin = H)
Initial settings stateNote1
User settings via command input (1) LCD bias set Note2 ADC select Note3 Common output status selection Note4
User settings via command input (2) Set on-chip resistance factor for VLC1 voltage regulator Note5 Electronic volume Note6
User settings via command input (3) Power control set Note7
End of initial settings Be sure to allow at least 700 ms between power control set and display ON (when the VLC1 to VLC5 smoothing capacitor is 0.22 F or less).Note10
LCD display screen settings Display start line set Note8 Writing screen data, etc.
Display ONNote9
40
Data Sheet S13368EJ3V0DS00
PD16682
Notes 1. See 11. RESET CIRCUIT. 2. See 12.11 LCD Bias Set. 3. See 12.8 ADC Select (Segment Driver Direction Select). 4. See 12.15 Common Output Status Select. 5. See 12.17 Set On-chip Resistance Factor for VLC1 Voltage Regulator. 6. See 12.18 Electronic Volume (Two-Byte Command). 7. See 12.16 Power Control Set. 8. See 12.2 Display Start Line Set. 9. See 12.1 Display ON/OFF. 10. This period changes depending on the panel characteristics and the capacitance of the booster/smoothing capacitor. It is recommended to determine this value after sufficient evaluation using the actual device.
13.2 Example of power OFF When turning the power of the IC off in the normal operation state (liquid crystal display ON, on-chip power supply circuits operating), because there is electric charge remaining in the power supply level smoothing capacitor connected between the driver reference power supply pins (VLC1 to VLC5) and VSS, power continues to be supplied to the LCD drive circuit and voltage may be applied to the LCD panel from the SEG and COM pins. At this time, the LCD panel may momentarily display data. Moreover, because the visual quality of the LCD panel may be affected, be sure to turn off the power to the IC in the following sequence.
Normal operation state
Command input Power save Note1
Reset (/RES pin = L ) Note2
Power supply between VDD/VDD2 and VSS OFF
Notes1. See 12.20 Power Save (Compound Command). 2. Application of a reset is optional.
Data Sheet S13368EJ3V0DS00
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PD16682
14. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C, VSS = 0 V)
Parameter Symbol VDD VDD2 VDD2 VLCD VLC1-VLC5 VIN1 VOUT1 VI/O1 VIN2 VOUT2 TA Tstg Rating -0.3 to +6.0 -0.3 to +3.75 -0.3 to +5.0 -0.3 to +15.0, VDD VLCD -0.3 to VLCD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VLCD+0.3 -0.3 to VLCD+0.3 -40 to +85 -55 to +150 Unit V V V V V V V V V V C C
*
Supply voltage Supply voltage 2 (4x boost) Supply voltage 2 (3x boost) Driver supply voltage Driver reference supply input voltage Logic system input voltage Logic system output voltage Logic system input/output voltage Driver system input voltage Driver system output voltage Operating ambient temperature Storage temperature
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
Recommended Operating Range
Parameter Supply voltage Supply voltage 2 (4x boost) Supply voltage 2 (3x boost) Driver supply voltage Logic system input voltage Driver system input voltage Symbol VDD VDD2 VDD2 VLCD VIN VLC1-VLC5 MIN. 1.8 2.4 2.4 6 0 0 10 TYP. MAX. 4.5 3.0 4.0 12 VDD VLCD Unit V V V V V V
Remarks 1. When using an external power supply, be sure to maintain these relations: VSS < VLC5 < VLC4 < VLC3 < VLC2 < VLC1 VLCD 2. Maintain VDD VLCD when turning the power on or off.
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Data Sheet S13368EJ3V0DS00
PD16682
*
Electrical Characteristics (unless otherwise specified, TA = -40 to +85 C, VDD2 = 2.7 to 3.3 V, during 4x boost mode: VDD2 = 2.7 to 3.0 V, or during 3x boost mode: VDD2 = 2.7 to 4.0 V)
Parameter High-level input voltage Low-level input voltage High-level input current Low-level input current High-level output voltage Low-level output voltage High-level leakage current Symbol VIH VIL IIH1 IIL1 VOH VOL ILOH Except for D7(SI), D6(SCL), and D5 to D0 Except for D7(SI), D6(SCL), and D5 to D0 IOUT = -1.5 mA, except OSCOUT IOUT = 4 mA, except OSCOUT D7(SI), D6(SCL), and D5 to D0 VIN/OUT = VDD Low-level leakage current ILOL D7(SI), D6(SCL), and D5 to D0 VIN/OUT = VSS Common output ON resistance Segment output ON resistance Driver voltage (boost voltage) RCOM RSEG VLCD VLCn COMn, VLCD 3VDD2, ILOL = 50 A VLCn SEGn, VLCD 3VDD2, ILOL = 50 A During 3x boost During 4x boost Current consumption (normal mode) IDD11 fOSC = 22 kHz, all display OFF data output, VDD = VDD2 = 3.0 V during 3x boost mode, TA = 25 C fOSC = 22 kHz, all display OFF data output, VDD = VDD2 = 3.0 V during 4x boost mode, TA = 25 C Current consumption (high-power mode) IDD12 fOSC = 22 kHz, all display OFF data output, VDD = VDD2 = 3.0 V during 3x boost mode, TA = 25 C fOSC = 22 kHz, all display OFF data output, VDD = VDD2 = 3.0 V during 4x boost mode, TA = 25 C Current consumption (standby mode) Current consumption (sleep mode) Oscillation frequency fOSC IDD22 IDD21 fOSC = 22 kHz, VDD = VDD2 = 3.0 V, TA = 25 C all display OFF data output, VDD = VDD2 = 3.0 V TA = 25 C, VDD = VDD2 = 3.0 V 10 % 17 22 25 kHz 0.2 5 7 15 153 230 104 190 78 135 2.7 VDD 3.6 VDD 55 2 4 3.0 VDD 4.0 VDD 110 k k V V -10 VDD - 0.5 0.5 10 Condition MIN. 0.8 VDD 0.2 VDD 1 -1 TYP.
Note
MAX.
Unit V V
A A
V V
A A
A
A
A
A
A A
Note The TYP. value is a reference value when TA = 25 C
Data Sheet S13368EJ3V0DS00
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PD16682
Required timing conditions (unless otherwise specified, TA = -40 to +85 C) 80 Series MPU
A0 tAS8 /CS1 (CS2="1") tCYC8 tCCLW, tCCLR tf tr tAH8
/WR, /RD tCCHR, tCCHW tDS8 D0 - D7 (Write) tACC8 D0 - D7 (Read) tOH8 tDH8
( VDD = 2.7 to 4.5 V )
Parameter Address hold time Address setup time System cycle time Control L pulse width (/WR) Control L pulse width (/RD) Control H pulse width (/WR) Control H pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF 10 A0 A0 Conditions MIN. 0 0 300 60 120 60 60 40 15 140 100 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C
44
Data Sheet S13368EJ3V0DS00
PD16682
( VDD = 2.4 to 2.7 V)
Parameter Address hold time Address setup time System cycle time Control L pulse width (/WR) Control L pulse width (/RD) Control H pulse width (/WR) Control H pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF 10 A0 A0 Conditions MIN. 0 0 1000 120 240 120 120 80 30 280 200 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC8-tCCLW-tCCHW) or (tr + tf) < (tCYC8-tCCLW-tCCHR). 2. All timing is rated based on 20 % or 80 % of VDD. 3. tCCLW and tCCLR are rated as the overlap time when /CS1 is at low level (CS2 = H) and /WR and /RD are also at low level.
Data Sheet S13368EJ3V0DS00
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PD16682
68 Series MPU
A0 R,/W tAS6 /CS1 (CS2="1") tCYC6 tEWHR, tEWHW tf tr tAH6
E tEWLR, tEWLW tDS6 D0 - D7 (Write) tACC6 D0 - D7 (Read) tOH6 tDH6
( VDD = 2.7 to 4.5 V )
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Read Write Enable L pulse width Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF E E E E 10 120 60 60 60 A0 A0 Conditions MIN. 0 0 300 40 15 140 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C
46
Data Sheet S13368EJ3V0DS00
PD16682
( VDD = 2.4 to 2.7 V )
Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Read Write Enable L pulse width Read Write Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF E E E E 10 240 120 120 120 A0, R,/W A0, R,/W Conditions MIN. 0 0 1000 80 30 280 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) (tCYC6-tEWLW-tEWHW) or (tr + tf) (tCYC6-tEWLR-tEWHR). 2. All timing is rated based on 20 % or 80 % of VDD. 3. tEWHW and tEWLW are rated as the overlap time when /CS1 is at low level (CS2 = H) and E is at high level. 4. D0 to D7 change to output regardless of the state of the E signal when R,/W becomes H in the state of /CS1 = L, CS2 = H ( See 5.1.2. (2) 68 Series Parallel Interface.).
Data Sheet S13368EJ3V0DS00
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PD16682
Serial Interface
tCSS /CS1 (CS2="1") tSAS tSAH tCSH
A0 tSCYC tSLW
SCL tf tr tSDS tSDH tSHW
SI
( VDD = 2.7 to 4.5 V )
Parameter Shift clock cycle SCL H pulse width SCL L pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH SCL SCL SCL A0 A0 SI SI /CS1,CS2 /CS1,CS2 Conditions MIN. 250 100 100 150 150 100 100 150 150 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C
48
Data Sheet S13368EJ3V0DS00
PD16682
( VDD = 2.4 to 2.7 V )
Parameter Shift clock cycle SCL H pulse width SCL L pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH SCL SCL SCL A0 A0 SI SI /CS1,CS2 /CS1,CS2 Conditions MIN. 400 150 150 250 250 150 150 250 250 TYP.
Note
MAX.
Unit ns ns ns ns ns ns ns ns ns
Note The TYP. value is a reference value when TA = 25 C Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 % or 80 % of VDD. Common
Parameter Oscillation frequency Symbol fCL Conditions CL, When using external input, VDD = VDD2 = 3.0 V 10 %, TA = 25 C MIN. 17 TYP. 22 MAX. 25 Unit kHz
Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. The frame time can be determined using the following equation. 1 frame = 1/fOSC or 1/fCL x 4 x duty value Therefore, when fOSC and fCL = 22 kHz and the duty value is 1/65: 1 frame = 45.5 s x 4 x 65 = 11.8 ms (approximately 84.6 kHz)
Data Sheet S13368EJ3V0DS00
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PD16682
Output timing for display output control
CL (out) tDFR
FR
( VDD = 2.7 to 4.5 V )
Parameter FR delay time Symbol tDFR Conditions FR, CL = 50 pF MIN. TYP.
Note
MAX. 80
Unit ns
20
Note The TYP. value is a reference value when TA = 25 C ( VDD = 2.4 to 2.7 V )
Parameter FR delay time Symbol tDFR Conditions FR, CL = 50 pF MIN. TYP.
Note
MAX. 200
Unit ns
50
Note The TYP. value is a reference value when TA = 25 C Remark All timing is rated based on 20 % or 80 % of VDD.
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Data Sheet S13368EJ3V0DS00
PD16682
Reset input timing
tRW /RES tR
Internal status
During reset
Reset completed
( VDD = 2.7 to 4.5 V )
Parameter Reset time Reset L pulse width Symbol tR tRW /RES 1.0 Conditions MIN. TYP.
Note
MAX. 1.0
Unit
s s
Note The TYP. value is a reference value when TA = 25 C ( VDD = 2.4 to 2.7 V )
Parameter Reset time Reset L pulse width Symbol tR tRW /RES 1.5 Conditions MIN. TYP.
Note
MAX. 1.5
Unit
s s
Note The TYP. value is a reference value when TA = 25 C Remark All timing is rated based on 20 % or 80 % of VDD.
Data Sheet S13368EJ3V0DS00
51
PD16682
15. STANDARD TCP PACKAGE DRAWING ( PD16682N-xxx-051)(1/3)
52
Data Sheet S13368EJ3V0DS00
PD16682
STANDARD TCP PACKAGE DRAWING ( PD16682N-xxx-051)(2/3)
Detail of hole
Detail of Hole 0.2 2-R0.5 2-R0.6 Cu Hole PI Hole
1.2 PI Hole
2-R0.8 Cu 1 Cu Hole
1.6 Cu
Detail of alignment mark
Detail of Alignment Mark
0.05
0.3
31.175 Mark to Mark
8.8 From P.C.
0.6
0.05
TCP tape winding method
Output lead
Winding direction
Tape pullout direction
Copper pattern on back side of tape
Data Sheet S13368EJ3V0DS00
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PD16682
STANDARD TCP PACKAGE DRAWING ( PD16682N-xxx-051)(3/3)
Pin configuration
No.1 No.2 No.3 No.4 No.5 No.6 No.7 No.8 No.9 No.10 No.11 No.12 No.13 No.14 No.15 No.16 No.17 No.18 No.19 No.20 No.21 No.22 No.23 No.24 No.25 No.26 No.27 No.28 No.29 No.30 No.31 No.32 No.33 No.34 No.35 No.36 No.37 No.38 No.39 No.40 No.41 No.42 No.43 No.44 No.45 No.46 No.47 No.48 No.49 No.50 No.51 No.52 No.53 No.54 No.55 No.56 No.57 No.58 No.59 No.60 No.61
NC FRS FR CL /DOF TESTOUT VSS' /CS1 CS2 VDD' /RES A0 VSS'
/WR, R,/W
/RD,E VDD' D0 D1 D2 D3 D4 D5 D6,SCL D7,SI VDD VDD2 VLCD VSS C1+ C1- C2+ C2- C3+ C3- VSS' VDD' VRS VR VLC1 VLC2 VLC3 VLC4 VLC5 VSS' TEST1 TEST2 TEST3 TEST4 TEST5 VDD' M,/S CLS VSS' C86 P,/S VDD' HPM VSS' IRS VDD' NC
DIE : FACE UP
NC NC NC COMS COM63 COM62 COM61 COM60 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * COM27 COM28 COM29 COM30 COM31 NC NC NC
No.1 No.2 No.3 No.4 No.5 No.6 No.7 No.8 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * No.197 No.198 No.199 No.200 No.201 No.202 No.203 No.204
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Data Sheet S13368EJ3V0DS00
PD16682
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S13368EJ3V0DS00
55
PD16682
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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